1. Field of the Invention
Embodiments of the invention relate to digital circuit design. More particularly, embodiments relate to scan chains of digital circuits.
2. Description of the Related Art
Circuit technologies of design for testability (DFT) have been steadily advanced for efficiently testing integrated circuits. A scan test is widely used for testing digital circuits. The scan test is conducted by replacing normal flip-flops with scan flip-flops and forming one or more shift chains with the scan flip-flops. In the scan test mode, a testing operation is carried out by repeating three steps of shift input, parallel loading, and shift output.
There are two kinds of scan chains, i.e., single scan chain and multi-scan chain. The single scan chain is formed by arranging all scan flip-flops in one chain. The multi-scan chain is formed by arranging the scan flip-flops in a plurality of chains. The multi-scan chain is generally used more than the single scan chain because it is advantageous for reducing a size of scan test vector.
All scan flip-flops of a scan chain operate at the same time when the scan chain is being conductive. As a result of the simultaneous operation of all the scan flip flops in a scan chain, there may be a transient voltage drop at a power source voltage. Such a transient voltage drop affects operating times. For example, such a transient voltage drop increases a setup time and a hold time. A longer setup time can be repaired by reducing a clock speed. However, a longer hold time cannot be corrected even by adjusting the clock speed.
Therefore, it results in a fail due to the scan test vector.